Embodiments of the disclosed technology relate to a liquid crystal display (LCD) and an array substrate.
Thin film transistor liquid crystal displays (TFT-LCDs) have the characteristics of small volume, low power consumption, no radiation and so on, and have prevailed in the present market of flat displays. However, liquid crystal displays have the disadvantage of relatively narrow viewing angle, thus the manufacturers developed various wide viewing angle technologies. Among the wide viewing angle technologies, advanced-super dimensional switching technology (AD-SDS) forms a multi-dimensional electric field including a parallel electric field generated between the sides (edge portions) of the pixel electrodes within a same plane and a longitudinal electric field generated between the pixel electrode layer and the common electrode layer on different layers, which enables all liquid crystal molecules between the pixel electrode and above the electrodes within the liquid crystal cell to rotate so as to enhance the work efficiency of the plane orientation liquid crystal and increase light transmittance. AD-SDS technology can be used to improve the display quality of TFT-LCDs, and has the advantages of high transmittance, wide viewing angle, high aperture ratio, low color aberration, small response time, no push Mura, etc.
In order to reduce production cost, the number of mask processes (i.e., the number of the mask used or the number of photolithography process) was reduced during the preparation process of the TFT-LCD array substrates of the AD-SDS type. Presently, manufacturers are actively developing 4-mask process to prepare the TFT-LCD array substrates of the AD-SDS type. As shown in FIGS. 1, 2 and 3, a conventional method comprises the following processes. The first mask process: a first transparent electrode layer and a gate metal layer are deposited on a glass substrate 1, exposure is conducted with a gray scale mask plate in a gray scale mask process, and etching, ashing, and removing processes are conducted to form the first layer transparent common electrode 2, a gate metal line 3 (including gate electrode (Gate)), two gate metal common electrodes (the gate metal common electrode 11′ in one row and the gate metal common electrode 12′ in a previous row). The second mask process: on the formed pattern described above, a gate insulation layer, a semiconductor layer, a doped semiconductor layer and a source/drain metal layer are sequentially deposited, then exposure is conducted with a gray scale mask plate in using a gray scale mask process, and etching, ashing, and removing processes are conducted to form a gate insulation layer 4, a semiconductor layer 5 (semiconductor active silicon island), a doped semiconductor layer 6 and a source/drain metal layer 7 (including source electrodes, drain electrodes, and data lines). The third mask process: a passivation insulation layer 8 (via hole layer) is deposited on the source/drain metal layer 7 and covers the entire glass substrate 1, and then via holes 10′ and 14′ are formed in the passivation insulation layer 8 by the process of exposure and etching. The fourth mask process: a transparent electrode layer is deposited on the substrate, a second layer of transparent pixel electrode 9 and a second layer transparent common electrode 13 are formed by the process of exposure and etching with a gray scale mask process. The pixel electrode 9 is connected with one of the source and drain electrodes by the via hole 10′; the second layer transparent common electrode 13 is connected with both the common electrodes 11′ and 12′ in two adjacent pixel rows by via holes 14′. In the area connecting the common voltage signals of the pixels in the present and previous lines (as shown in FIG. 3), the cross-section of via holes 14′ is U-shaped or square-shaped, the bottom side is in contact with the gate metal common electrodes 11′, 12′, under which the first layer transparent common electrode 2 is formed and not in contact with the via hole 14′.
The conventional technology employs amorphous indium tin oxide (a-ITO) thin film in preparing the first layer transparent common electrode with a gray scale mask plate; when the film for forming the next gate insulation layer 4 is deposited, the temperature is typically of above 300 degree Celsius. The a-ITO thin film will undergo a crystallization reaction under such a high temperature and be converted into polycrystalline indium tin oxide (p-ITO) thin film. Since the crystal grains of p-ITO are different in size from those of the gate metal common electrode 11′, 12′, it will result in strip and delamination between the first layer transparent common electrode 2 and the gate metal common electrode 11′, 12′ during the course of a-ITO being converted into p-ITO (as shown in FIG. 4), and cracks or gaps 15 appear. Such gaps 15 can cause poor contact, thus the voltage signals over the gate metal common electrode 11′, 12′ can not be transferred to the first layer transparent common electrode 2 effectively, such that in the adjacent pixel rows, the first layer transparent common electrode of the previous pixel row and the first layer transparent common electrode of the present pixel row can not work normally, which results in the abnormality of the pixel operation and affects the display effect and display quality.